Then to overcome these two fundamental design problems with the SR flip-flop design, the JK flip Flop was developed. if Set or Reset change state while the enable (EN) input is high the correct latching action may not occur the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided Unlike the JK Flip-flop, the basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic circuits but it suffers from two basic switching problems.
